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Program Status Register

The PSR on the Cortex-M3 differs slightly from other ARM processors. The basic arithmetic status flags are in the same positions, and the Thumb (T) bit is present as on any Thumb ISA processor. With the Cortex-M3, the T bit is always set because the processor can only execute in Thumb mode.

CM3_PSR.png

N – Negative Flag

Z – Zero Flag

C – Carry Flag

V – Overflow Flag

Q – Sticky Saturation Flag

ICI/IT Bits

As ICI bits (Interruptible Continuable Instructions), these bits are used to store state for multi-cycle instructions that can be interrupted and then continue after an interrupt.

On the Cortex-M3 the load-multiple (LDM) and store-multiple (STM) multi-cycle instructions are interruptible. This has an advantageous effect on interrupt latency over earlier ARM implementations, which traditionally just blocked until these instructions completed (ARM7TDMI).

As IT bits (If-Then), these bits are used to store the number of instructions in an ‘IF-THEN’ block, and the condition for execution. Cortex-M3 has IF-THEN instruction blocks that effectively replace the conditional execution of each instruction that the original 32-bit ARM instruction set had.

ISR Number

The ISR-Number is only on the Cortex-M3 with it’s sophisticated built-in exception model. The number of the exception that has been pre-empted is stored in here.

CortexM3PSR (last edited 2008-09-06 09:06:41 by support)