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ARM Cortex-M3 Processor

Serial Wire Debug Pins

Cortex-M3 is the first ARM core to implement the Serial Wire Debug Interface in addition to the more traditional JTAG interface. This is designed to reduce the pin count required for debug from the 5 used by JTAG (including GND) down to 3. In addition, one of the pins freed up by this can be used for Single Wire Viewing (SWV), which is a low cost tracing technology. The SWD/SWV pins are overlaid on top of the JTAG pins as follows:

SWD_JTAG_PINS.png

There are special sequences defined to switch from JTAG mode (default) and SWD mode that can sent to the core through just the SW pins.

Cortex-M3 Memory Map

Unlike any other ARM processor, Cortex-M3 has a ‘structured’ memory map. This is particular to V7-M of the ARM architecture and is not for example in V7 in general. The 4GB range that is available through the 32-bit address space is broadly structured as shown below:

M3-MemoryMap.png

CortexM3 (last edited 2008-09-04 23:22:02 by support)