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Important Information for users of NXP LPCXpresso

This site is for users of Code Red branded products.

NXP LPCXpresso users should visit the LPCXpresso FAQ's for up-to-date information relevant to that product.

Bit-Banding

MCU's based on the Cortex-M3 can optionally implement a feature known as "bit-banding". This allows an individual bit in an SRAM location or peripheral register to be set/cleared by a single store/load instruction to a bit-band aliased memory address, rather than using a conventional read/modify/write instruction sequence.


Type

Address range

Bit-band alias address range

SRAM

0x20000000-0x200FFFFF

0x22000000-0x23FFFFFF

Peripheral

0x40000000-0x400FFFFF

0x42000000-0x43FFFFFF

There are no special compiler extensions in the Code Red tools to support the use of bit-banding, but it is easy to write C macros to handle bit-banding in a straightforward way.

The below ZIP file contains an NXP LPC1768 example project providing sample implementations of such macros and their use. Note that this example uses the semihosting mechanism to display information to the debugger console. It also assumes that the CMSISv1p30_LPC17xx library project is available in the same workspace. This project can be found in the examples subdirectory of your Code Red tools installation directory.

Please see the documentation for the MCU that you are using to see whether support for bit-banding is included. But note that NXP's LPC13xx MCUs do not support bit-banding, whereas the LPC17xx MCUs do.

For more general information on bit-banding, please see ARM's processor documentation.

BitBanding (last edited 2011-09-20 12:55:28 by CrSupportAb)